1. Field of the Invention
This invention relates to an analog to digital converter which includes a plurality of comparators for comparing an analog input voltage with comparison voltages as reference voltages having different voltage values, and more particularly to an analog to digital converter of the type mentioned which includes an ECL circuit which is used in an emitter follower circuit or a processing circuit employed at an input stage of each comparator.
2. Description of the Related Art
An analog to digital converter of the parallel comparison type called a flash analog to digital converter having a construction wherein a number of comparators, which have comparison voltages of different voltage values equal to the number of bits of a digital signal, are arranged for collectively determining the comparison voltages to find a reference voltage equal to an analog input voltage, commonly employs, at an input stage of each of the comparators, an emitter follower circuit which has the characteristics that the input impedance is comparatively high and that it is superior in interference suppressing capability for the preceding and following stages.
An example of the construction of an analog to digital converter of the parallel comparison type is shown in FIG. 1. Referring to FIG. 1, a reference voltage generation circuit 1 includes, where a digital signal is constituted from, for example, 8 bits, 256 resistors r.sub.1 to r.sub.256 connected in series, for example, between lines V.sub.RT and V.sub.RB and generates reference voltages of different voltage values at 255 junctions between adjacent ones of the resistors by potential division of the resistors.
The reference voltages serve as comparison voltages for 255 comparators COP1, . . . of a comparison circuit 2. An analog input voltage V.sub.IN is inputted commonly as an object voltage for comparison to the 255 comparators COP1, . . . . The 255 comparators COP1, . . . collectively determine one of the comparison voltages which is equal to the input voltage VIN.
The comparison outputs of the comparators COP1, . . . are supplied by way of a gate circuit 3 to an encoder 4, by which they are converted into a digital signal D1 to D8 of 8 bits to be outputted.
A conventional example of the circuit construction of the comparators of the analog to digital converter of the parallel comparison type described above is shown in FIG. 2.
Referring to FIG. 2, an NPN transistor Q1 of an emitter follower stops to the base of which an analog input voltage V.sub.IN is inputted, another NPN transistor Q2 to the base of which a bias voltage V.sub.BIAS is inputted and a resistor R1 are connected in series between a GND line and a V.sub.EE line to construct an emitter follower stage 11 on the analog input side.
A further NPN transistor Q3 of another emitter follower to the base of which a reference voltage V.sub.REF is inputted, a still further NPN transistor Q4 to the base of which the bias voltage V.sub.BIAS is inputted and another resistor R2, are connected in series between the GND line and the V.sub.EE line to construct an emitter follower stage 12 on the reference voltage input side.
Meanwhile, a pair of differential transistors Q5 and Q6 whose emitters are connected common to perform a differential operation, a pair of resistors R3 and R4 connected between the collectors of the differential transistors Q5 and Q6 and the GND line, respectively, and a constant-current transistor Q7 and a resistor R5 connected in series between a common junction between the emitters of the differential transistors Q5 and Q6 and the V.sub.EE line construct a differential amplifier 13.
In the differential amplifier 13, the analog input voltage V.sub.IN is applied by way of the emitter follower stage 11 to the base of the transistor Q5 of the differential transistor pair, and the reference voltage V.sub.REF is applied to the other transistor Q6 by way of the emitter follower stage 12. Comparison outputs are thus led out from the collectors of the differential transistors Q5 and Q6.
Subsequently, a second related art will be described.
An ECL output circuit having such a construction as shown in FIG. 3 is conventionally known as an ECL output circuit which has a power saving function.
Referring to FIG. 3, a pair of differential transistors Q11 and Q12 whose emitters are connected in common to perform a differential operation, a pair of resistors R11 and R12 connected between the collectors of the differential transistors Q11 and Q12 and a GND terminal 21, and a transistor Q13 and a resistor R13 connected in series between a common junction between the emitters of the differential transistors Q11 and Q12 and a V.sub.EE power source terminal 22, respectively, construct a differential amplifier 23.
In the differential amplifier 23, the bases of the differential transistors Q11 and Q12 are connected to input terminals 24 and 25, respectively.
During power saving (PS) operation, a PS Signal is supplied to a reference voltage circuit 27 by way of a control terminal 26. The reference voltage circuit 27 applies, when a power saving operation is not to be performed, a predetermined reference voltage to the base of the transistor Q13 to turn the transistor Q13 into an on-state, but when a power saving operation is to be performed, the reference voltage circuit 27 turns the transistor Q13 into an off-state in response to the PS signal.
Two outputs of the differential amplifier 23 are supplied to another differential amplifier 30 at the last stage by way of a pair of emitter follower circuits 28 and 29.
The emitter follower circuit 28 includes a transistor Q14 whose collector is connected to the GND terminal 21 and whose base receives one of the two outputs of the differential amplifier 23, another transistor Q15 connected in a diode connection with the collector and the base thereof connected in common to the emitter of the transistor Q14, and a further transistor Q16 and a resistor R14 connected in series between the emitter of the transistor Q15 and the V.sub.EE power source terminal 22.
The emitter follower circuit 29 similarly includes a transistor Q17, another transistor Q18 connected in a diode connection, a further transistor Q19 and a resistor R15.
A predetermined bias voltage V.sub.BIAS is applied from a variable voltage source 31 to the bases of the transistors Q16 and Q19.
The differential amplifier 30 includes a pair of differential transistors Q20 and Q21 whose emitters are connected in common to perform a differential operation, a resistor R16 connected between the collector of the transistor Q21 and the GND terminal 21, and a transistor Q22 and a resistor R17 connected in series between a common junction between the emitters of the differential transistors Q20 and Q21 and the V.sub.EE power source terminal 22.
The predetermined bias voltage V.sub.BIAS from the variable voltage source 31 is applied also to the base of the transistor Q22. The variable voltage source 31 is constructed so as to stop, upon power saving operation, generation of the bias voltage V.sub.BIAS in response to a PS signal. Consequently, during power saving operation, the transistors Q16, Q19 and Q22 are put into an off-state.
The collector output of the transistor Q21 is led out from an output terminal 32 by way of an output transistor Q23.
In the emitter follower circuit 11 at the analog input stage of the construction described above in FIG. 2, since the emitter of the transistor Q1 has a parasitic capacitance C.sub.p, there is a problem in that, if the through rate of the input voltage V.sub.IN is high, then the base-emitter voltage V.sub.BE of the transistor Q1 is varied by a charging or discharging current flowing through the parasitic capacitance C.sub.p, which gives rise to distortion in the emitter voltage of the transistor Q1.
Meanwhile, in the analog to digital converter of the parallel comparison type, a number of, for example, 255 in the case of 8 bits, comparators of the construction wherein the emitter follower stages 11 and 12 and the differential amplifier 13 are provided in a one by one corresponding relationship are arranged in parallel to the analog input voltage V.sub.IN.
However, in the comparator of the construction described above, since high currents flow, upon switching of the differential amplifier 13, through the bases of the differential transistors Q5 and Q6 and such current changes have a significant influence on the emitter current of the emitter follower stage 11, the conversion accuracy in analog to digital conversion is deteriorated.
In order to reduce the influence of kickback noise from the differential amplifier, the current to flow through the emitter follower stage 11 should be increased in. This, however, will give rise to an increase the current consumption.
In an ideal analog to digital converter, an analog input voltage has the width of one LSB (Least Significant bit) for one digital code. In an actual analog to digital converter, the width may be greater or smaller than one LSB. The variation in width appears as a differential linear distortion (DLE).
In order to reduce the differential linear distortion in the analog to digital converter of the parallel comparison type of the construction described above, it is required to effectively reduce the difference .DELTA.V.sub.BE between the base-emitter voltages V.sub.BE of the transistors Q1 and Q3 of the emitter follower stages 11 and 12 constituting the input stages of each comparator.
A conventional countermeasure for such effective reduction of the difference .DELTA.V.sub.BE between the base-emitter voltages V.sub.BE of the transistors Q1 and Q3 of the emitter follower stages 11 and 12 is to increase the size of each of the transistors Q1 and Q3.
However, if the transistors Q1 and Q3 of the emitter follower stages 11 and 12 are increased in size, then another problem takes place in that the input capacitance which has a significant influence on the conversion rate upon analog to digital conversion is increased, resulting in deterioration of the conversion accuracy.
Besides, since the difference .DELTA.V.sub.BE cannot be reduced below a limit provided by a process, there is a limitation in reduction of the differential linear distortion.
Further, in the ECL output circuit of the related art of the construction described above in FIG. 3, there is a problem in that, when the power saving function operates, the output level of the output transistor Q23 rises to a high level, resulting in an increase of the power dissipation at the terminal end of the output.
In particular, when the bias voltage V.sub.BIAS of the variable voltage source 31 approaches V.sub.EE during power saving operation, the transistor Q22 is turned into an off-state. Consequently, only the base current of the output transistor Q23 flows through the resistor 16 so that the base potential of the transistor Q23 becomes substantially equal to 0 V, and as a result, the output level of the transistor Q23 changes to a high level.
Here, if it is assumed that the present circuit terminates, for example, in a V.sub.TT power source of -2 V by way of a resistor of 50.OMEGA. as indicated by a dotted line in FIG. 3, then when the high level is -0.9 V, since the potential difference between the opposite ends of the resistor of 50.OMEGA. is 1.1 V, a current of 22 mA flows through the resistor of 50.OMEGA., but when the low level is -1.8 V, since the potential difference between the opposite ends the resistor of 50.OMEGA. is 0.2 V, a current of 4 mA flows through the resistor of 50.OMEGA..
Accordingly, between the high level output and the low level output, a power dissipation difference of 36 mW (=18 mA.times.2 V) is produced for each output terminal.